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general description the MAX14521E is a quad-output high-voltage dc-ac converter that drives four electroluminescent (el) lamps. the device features a 2.7v to 5.5v input range that allows the device to accept a variety of voltage sources such as single-cell lithium-ion (li+) batteries. the lamp outputs of the device generate up to 300v p-p for maximum lamp brightness. the high-voltage outputs are esd protected up to ?5kv human body model (hbm), ?kv contact discharge, and ?kv air gap discharge, as specified in iec 61000-4-2. the MAX14521E uses a high-voltage full-bridge output stage to convert the high voltage generated by the boost converter to a sinusoidal output waveform. the MAX14521E utilizes a high-frequency spread-spectrum oscillator to reduce the amount of emi/efi generated by the boost-converter circuit. the MAX14521E provides an i 2 c interface to set the boost converter and el output switching frequencies through an 8-bit register and the peak output voltages with 5 bits of resolution. the MAX14521E also provides an adjustable automatic ramping feature that slowly increases or decreases the peak output voltage when a change is made to the output amplitude. the slew rate of the automatic ramp is set with 3 bits of resolution through the i 2 c interface and it is independent for each channel. the MAX14521E features an audio auxiliary input aux that modulates the el output voltage and fre- quency for dynamic lighting effects. the MAX14521E is available in a small, 4mm x 4mm, 24-pin tqfn package, and specified over the extend- ed -40? to +85? operating temperature range. applications keypad backlighting lcd backlighting pdas smartphones automotive instruments clusters features ? 300v p-p maximum output for highest brightness ? esd-protected el lamp outputs ?5kv human body model ?kv iec 61000-4-2 contact esd protection ?kv iec 61000-4-2 air gap discharge ? 2.7v to 5.5v input voltage range ? i 2 c interface for control of brightness, el frequency, boost frequency, shape ? sinusoidal output for low audible noise ? individual dimming control ? individually adjustable output brightness ramping rate ? ?% el output frequency accuracy for truest el panel color ? audio input for dynamic lighting effects ? spread-spectrum boost converter ? 100na shutdown current ? space-saving, 4mm x 4mm, 24-pin tqfn package MAX14521E quad, high-voltage el lamp driver with i 2 c interface ________________________________________________________________ maxim integrated products 1 MAX14521E cs l x d 3 c cs 0.1 f pgnd 6 lx 5 10 f c sn 330pf v bat r sn 20 sda 10 scl 11 a0 7 a1 8 to baseband/pmic rb 12 15 gnd 9 v dd 1 el1 el lamp1 23 el2 el lamp1 19 el3 el lamp1 17 el4 el lamp1 21 com 13 aux audio line-in v dd typical operating circuit 19-4477; rev 0; 2/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package MAX14521Eetg+ -40? to +85? 24 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. pin configuration appears on last page
MAX14521E quad, high-voltage el lamp driver with i 2 c interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +5.5v, total c lamp = 10nf, c cs = 3.3nf, tapped inductor = 2.3?/115?, 1:7 ratio (i sat = 0.7a, r s = 1 ), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25? and v dd = 3.7v.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . (all voltages referenced to gnd, unless otherwise noted.) v dd ........................................................................-0.3v to +6.0v cs, el1, el2, el3, el4, com..............................-0.3v to +160v lx ...........................................................................-0.3v to +33v rb, a0, a1, aux....................................................-0.3v to +6.0v scl, sda....................................................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70?) 24-pin tqfn-ep (derate 27.8mw/? above +70?)..2222mw package junction-to-ambient thermal resistance ( ja ) (note 1) ........................................................................36?/w package junction-to-case thermal resistance ( jc ) (note 1) ..........................................................................3?/w operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units input voltage v dd 2.7 5.5 v battery voltage v bat (note 3) 13.2 v input supply current i dd all channels on, 300v p-p , f el = 200hz, sine- wave output shape 350 900 ? t a = +25? 25 100 shutdown supply current i shdn rb, a0, a1 = 0v or v dd ; scl = sda = gnd or v dd ; not toggling t a = -40? to +85? 300 na shutdown tapped-inductor supply current i lx_shdn 2100 na undervoltage lockout v uv v dd rising 1.6 2.0 2.5 v uvlo hysteresis v uv_hyst 70 mv el outputs (el_, com) v e l_ - v c om ; e l_ _[ 4:0] = 01000; v d d = 3.7v 66 78 90 v e l_ - v c om ; e l_ _[ 4:0] = 10000; v d d = 3.7v 136 154 172 peak-to-peak output voltage v p-p v e l_ - v c om ; e l_ _[ 4:0] = 11111; v d d = 3.7v 268 300 320 v max average output voltage v avg v el_ - v com 1v el_ high-side switch on-resistance r onhs_el_ 1270 el_ low-side switch on-resistance r onls_el_ 700 com high-side switch on-resistance r on hs_com 390 com low-side switch on-resistance r on ls _c om 175
MAX14521E quad, high-voltage el lamp driver with i 2 c interface _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units el_ high-side switch off- leakage i lkghs_el_ -1 +1 ? el_ low-side switch off- leakage i lkgls_el_ -1 +1 ? com high-side switch off- leakage i lkghs _com -1 +1 ? com low-side switch off- leakage i lkgls _com -1 +1 ? t a = +25? 194 200 206 f el_lr fel[7:0] = 1000 0000; v dd = 3.7v t a = -40? to +85? 186 200 212 t a = +25? 388 400 412 el lamp switching frequency f el_hr fel[7:0] = 1011 1111; v dd = 3.7v t a = -40? to +85? 376 400 424 hz boost converter el_ _[4:0] = 01000; v dd = 3.7v 33 39 45 el_ _[4:0] = 10000; v dd = 3.7v 68 77 86 peak output voltage v cs el_ _[4:0] = 11111; v dd = 3.7v 134 150 160 v fsw[4:0] = 10000 400 fsw[4:0] = 11111 800 fsw[4:0] = 00000 (default) 800 tapped-inductor center switching frequency f sw fsw[4:0] = 01111 1600 khz tapped-inductor switching frequency spreading factor s f ss[1:0] = 01, 10, or 11 8 % tapped-inductor switching frequency modulation frequency f m ss[1:0] = 11 f sw /128 khz switch on-resistance r lx i sink = 25ma, v dd = 3.7v 3 lx current i lx v lx = 30v -1 +10 ? cs input current i cs no load, v cs = 150v 27 ? control input aux input range aux rng 0v dd v input capacitance aux cap 10 pf control input rb input logic-low voltage v il_rb 0.5 v input logic-high voltage v ih_rb 1.5 v input hysteresis i hys_rb 130 mv input leakage current i lkg_rb v rb = 5.5v or 0 -1 +1 a input capacitance c in 10 pf i 2 c interface logic (sda, scl, a1, and a0) (figure 1) input logic-low voltage v il 0.5 v input logic-high voltage v ih 1.5 v input hysteresis i hys 130 mv electrical characteristics (continued) (v dd = +2.7v to +5.5v, total c lamp = 10nf, c cs = 3.3nf, tapped inductor = 2.3?/115?, 1:7 ratio (i sat = 0.7a, r s = 1 ), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25? and v dd = 3.7v.) (note 2)
MAX14521E quad, high-voltage el lamp driver with i 2 c interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +2.7v to +5.5v, total c lamp = 10nf, c cs = 3.3nf, tapped inductor = 2.3?/115?, 1:7 ratio (i sat = 0.7a, r s = 1 ), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25? and v dd = 3.7v.) (note 2) parameter symbol conditions min typ max units input leakage current i lkg -1 +1 ? output low voltage v ol i sink = 3ma 0.4 v input/output capacitance c i/o 10 pf serial-clock frequency f scl 400 khz clock low period t low 1.3 ? clock high period t high 0.6 ? bus free time t buf 1.3 ? start setup time t su,sta 0.6 ? start hold time t hd , sta 0.6 ? stop setup time t su , sto 0.6 ? data in setup time t su , dat 100 ns data in hold time t hd , dat 0 900 ns receive scl/sda minimum rise time t r 20 + 0.1c b ns receive scl/sda maximum rise time t r 300 ns receive scl/sda minimum fall time t f 20 + 0.1c b ns receive scl/sda maximum fall time t f 300 ns transmit sda fall time t f c b = 400pf 20 + 0.1c b 300 ns scl/sda noise suppression time t i 50 ns esd protection human body model ?5 iec 61000-4-2 contact discharge ? el_ , com iec 61000-4-2 air gap discharge ? kv thermal protection thermal shutdown t shdn 160 ? thermal shutdown hysteresis t hyst 12 ? note 2: all parameters are 100% production tested at t a = +25? and t a = +85?, unless otherwise noted. parameters at -40? are guaranteed by design. note 3: see the f sw selection section when v bat is above 5.5v.
MAX14521E quad, high-voltage el lamp driver with i 2 c interface _______________________________________________________________________________________ 5 total input current vs. supply voltage MAX14521E toc01 supply voltage (v) total input current (ma) 3.9 5.1 3.5 3.1 4.7 4.3 10 20 30 40 50 60 0 2.7 5.5 v fi = 300v p-p v fi = 200v p-p total input current vs. temperature MAX14521E toc02 temperature ( c) total input current (ma) 10 35 60 -15 40 44 48 52 56 60 16 20 24 4 8 12 28 32 36 0 -40 85 v fi = 300v p-p total input current vs. boost converter frequency MAX14521E toc03 boost converter frequency (khz) total input current (ma) 1000 1400 1200 800 600 20 40 60 80 0 400 1600 v fi = 300v p-p point where set v el decreases as frequency increases v fi = 200v p-p typical operating characteristics (v dd = 3.7v, total c lamp = 10nf, c cs = 3.3nf, l x = 2.3?/115?, 1:7 ratio, (i sat = 0.7a, r s = 1 ), t a = +25?, sine-wave output, f sw = 800khz, f el = 200hz, unless otherwise noted.) scl sda start condition stop condition repeated start condition start condition t hd, sta t su, sta t hd, sta t buf t su, sto t low t su, dat t hd, dat t high t r t f figure 1. i 2 c timing specifications total input current vs. load MAX14521E toc04 total combined load (nf) total input current (ma) 40 20 60 40 80 120 160 200 0 080 v el = 250v p-p , f sw = 800khz, unless otherwise noted v dd = 5v f sw = 700khz v dd = 3.3v f sw = 400khz v el = 200v p-p shutdown current vs. supply voltage MAX14521E toc05 supply voltage (v) shutdown current (na) 3.9 5.1 3.5 3.1 4.7 4.3 0.5 1 1.5 2 0 2.7 5.5 shutdown current vs. temperature MAX14521E toc06 temperature ( c) shutdown current (na) 10 35 60 -15 10 100 1 0.1 -40 85
MAX14521E quad, high-voltage el lamp driver with i 2 c interface 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3.7v, total c lamp = 10nf, c cs = 3.3nf, l x = 2.3?/115?, 1:7 ratio, (i sat = 0.7a, r s = 1 ), t a = +25?, sine-wave output, f sw = 800khz, f el = 200hz, unless otherwise noted.) el switching frequency vs. supply voltage MAX14521E toc13 supply voltage (v) el switching frequency (hz) 3.9 5.1 3.5 3.1 4.7 4.3 195 200 205 210 190 2.7 5.5 el switching frequency vs. temperature MAX14521E toc14 temperature ( c) -15 10 60 35 -40 85 el switching frequency (hz) 195 200 205 210 190 v fi = 200v p-p boost converter frequency vs. fsw[4:0] MAX14521E toc15 fsw[4:0] code (decimal value) 12 8 41624 20 28 032 boost converter frequency (khz) 600 1000 1400 1800 400 200 800 1200 1600 0 peak-to-peak output voltage vs. supply voltage MAX14521E toc07 supply voltage (v) peak-to-peak output voltage (v) 3.9 5.1 3.5 3.1 4.7 4.3 160 170 200 210 220 180 190 230 240 250 150 2.7 5.5 v fi = 200v p-p c load = 10nf c load = 20nf peak-to-peak output voltage vs. temperature MAX14521E toc08 temperature ( c) peak-to-peak output voltage (v) 10 35 60 -15 205 210 195 200 190 -40 85 v fi = 200v p-p peak-to-peak output voltage vs. code MAX14521E toc09 el_ _[4:0] code (decimal value) peak-to-peak output voltage (v) 16 824 100 150 250 50 200 300 350 0 032 average output voltage vs. supply voltage MAX14521E toc10 supply voltage (v) average output voltage (mv) 4.7 4.3 5.1 3.9 3.1 3.5 -700 -500 -300 -800 -400 -100 0 -1000 -600 -200 -900 2.7 5.5 average output voltage vs. temperature MAX14521E toc11 temperature ( c) average output voltage (mv) -15 10 60 35 -700 -500 -300 -800 -400 -100 0 -1000 -600 -200 -900 -40 85 el switching frequency vs. fel[7:0] MAX14521E toc12 fel[7:0] code (decimal value) el switching frequency (hz) 192 64 128 300 500 700 200 600 900 1000 0 400 800 100 0 256
MAX14521E quad, high-voltage el lamp driver with i 2 c interface _______________________________________________________________________________________ 7 ramp time vs. code MAX14521E toc16 rt_ _[2:0] code (decimal value) ramp time (ms) 246 1500 2000 500 1000 0 08 normalized brightness vs. supply voltage MAX14521E toc17 supply voltage (v) normalized brightness 3.9 5.1 3.5 3.1 4.7 4.3 0.5 1 1.5 2 0 2.7 5.5 v fi = 200v p-p boost converter magnitude vs. frequency (spread spectrum disabled) MAX14521E toc18 frequency (mhz) boost converter magnitude (dbv) 10 -80 -60 -40 -20 0 -100 0100 rbw = 100hz f sw = 1.6mhz v el = 300v p-p ss[1:0] = 00 boost converter magnitude vs. frequency (spread spectrum enabled) MAX14521E toc19 frequency (mhz) boost converter magnitude (dbv) 10 -80 -60 -40 -20 0 -100 0 100 rbw = 100hz f sw = 1.6mhz v el = 300v p-p ss[1:0] = 10 scope shot with sl[1:0] = 00 MAX14521E toc20 math freq 201.7 hz math pk-pk 205 v scope shot with sl[1:0] = 01 MAX14521E toc21 math freq 201.3 hz math pk-pk 208 v typical operating characteristics (continued) (v dd = 3.7v, total c lamp = 10nf, c cs = 3.3nf, l x = 2.3?/115?, 1:7 ratio, (i sat = 0.7a, r s = 1 ), t a = +25?, sine-wave output, f sw = 800khz, f el = 200hz, unless otherwise noted.) scope shot with sl[1:0] = 10 MAX14521E toc22 math freq 201.8 hz math pk-pk 208 v scope shot with sl[1:0] = 11 MAX14521E toc23 math freq 202.0 hz math pk-pk 208 v ramping time MAX14521E toc24 math pk-pk 298 v v el 50v/div 1s/div
MAX14521E quad, high-voltage el lamp driver with i 2 c interface 8 _______________________________________________________________________________________ detailed description the MAX14521E is a quad-output high-voltage dc-ac converter that drives four el lamps. the device fea- tures a 2.7v to 5.5v input range that allows the device to accept a variety of sources such as single-cell li+ batteries. the lamp outputs of the device generate up to 300v p-p for maximum lamp brightness. the MAX14521E utilizes a high-frequency spread- spectrum boost converter that reduces the amount of emi/efi generated by the circuit. the boost-converter switching frequency is set with an 8-bit register through the i 2 c interface. the MAX14521E uses a high-voltage full-bridge output stage to convert the high voltage gen- erated by the boost converter to an ac waveform suit- able for driving an el lamp. an internal register controlled through the i 2 c interface sets the shape of the el output waveshape. the el output switching frequency for all outputs is set with an 8-bit register through the i 2 c interface. the MAX14521E provides a serial digital interface that allows the user to set the peak voltage of each output independently with 5 bits of resolution. the MAX14521E also provides an adjustable automatic ramping feature that slowly increases or decreases the peak output volt- age when the set value is changed. the slew rate of the ramp is set with 3 bits of resolution through the i 2 c interface and it is independent for each channel. the MAX14521E features an audio auxiliary input aux that modulates the el output voltage and frequency for dynamic lighting effects. the high-voltage outputs are esd protected up to ?5kv human body model, ?kv air gap discharge, and ?kv contact discharge, as specified in iec 61000-4-2. pin description pin name function 1 el1 high-voltage el panel output 1. connect el1 to segment 1 of the el lamp. 2, 4, 16, 18, 20, 22, 24 n.c. no connection. not internally connected. 3csfeed b ack c onnecti on. c onnect c s to the outp ut of the b oost conver ter ( cathod e of the r ecti fyi ng d i od e) . 5 lx internal switching dmos drain connection. connect lx to the middle terminal of the tapped inductor. 6 pgnd power ground. connect to gnd. 7a0 address input 0. address inputs allow up to four connections on one common bus. connect a0 to gnd or v dd . 8a1 address input 1. address inputs allow up to four connections on one common bus. connect a1 to gnd or v dd . 9v dd input supply voltage 10 sda open-drain, serial data input/output. sda requires an external pullup resistor. 11 scl serial-clock input. scl requires an external pullup resistor. 12 rb reset input. drive rb low to clear all registers to zero and put the device into a low-power shutdown mode. the device does not respond to i 2 c communications when rb is held low. 13 aux aud i o e ffects inp ut. m od ul ates am p l i tud e/fr eq uency of the e l outp ut w i th the au x i np ut vol tag e am p l i tud e. 14 i.c. internally connected. connect i.c. to gnd. 15 gnd ground 17 el4 high-voltage el panel output 4. connect el4 to segment 4 of the el lamp. 19 el3 high-voltage el panel output 3. connect el3 to segment 3 of the el lamp. 21 com high-voltage com output. connect com to common terminal of the el lamp. 23 el2 high-voltage el panel output 2. connect el2 to segment 2 of the el lamp. ep exposed pad. connect ep to gnd.
MAX14521E quad, high-voltage el lamp driver with i 2 c interface _______________________________________________________________________________________ 9 el output voltage the shape, slope, frequency, ramp-on/-off times, and peak-to-peak voltage of the MAX14521E lamp outputs are programmed using internal registers. the MAX14521E is capable of producing output wave- forms with varying shapes and slew rates. the user sets the shape and slew rate of the output using bits in the el shape registers. the MAX14521E el lamp output frequency uses an internal el oscillator to set the desired frequency. the output frequency is adjusted by the fel[7:0] bits of the el output frequency register. the el frequency increases and decreases linearly with fel[7:0]. the peak-to-peak voltage of the el lamp output is var- ied from 0 to 300v p-p by programming the el_ _[4:0] bits of the el ramping time and el peak voltage regis- ters. the peak-to-peak voltage increases and decreas- es linearly with el_ _[4:0]. the MAX14521E also features a slow fade-on and slow fade-off time feature programmed by the rt_ _ [2:0] bits of the el ramping time and el peak voltage regis- ters. this slow fade-on/-off feature causes the peak-to- peak voltage of the el outputs to slowly rise from the previously set value to the maximum set value. this fea- ture also causes the peak-to-peak voltage of the el outputs to fall from the maximum set value to zero when the device is placed into shutdown. the slow rise and fall of the peak-to-peak el output voltage creates a soft fade-on and fade-off of the el lamp. functional diagram v dd lx fel osc thermal shutdown v sense uvlo shdn no-operation signal f sw oscillator i 2 c aux sda scl a1 a0 el peak control cs dmos driver gnd pgnd spread spectrum and soft-start half h-bridge half h-bridge half h-bridge half h-bridge half h-bridge high esd prot high esd prot high esd prot high esd prot high esd prot shape control pwm converter rb el1 com el2 el3 el4 MAX14521E
boost converter the MAX14521E boost converter consists of an exter- nal-tapped inductor from v dd to the lx input, an inter- nal dmos switch, an external diode from the secondary of the tapped inductor to the cs output, an external capacitor from the cs output to gnd, and an el lamp connected to the el lamp outputs. when the dmos switch is turned on, lx is connected to gnd, and the inductor is charged. when the dmos switch is turned off, the energy stored in the inductor is transferred to the capacitor c cs and the el lamp. note: the MAX14521E exhibits high-voltage spikes on the lx node. the addition of a snubber circuit to the lx node protects the device by suppressing the high- voltage spikes. the values of r sn and c sn should be optimized for the specific tapped inductor used. typical values are r sn = 20 and c sn = 330pf. the MAX14521E boost-converter frequency uses an internal oscillator to set the frequency of the boost con- verter. the oscillator frequency is adjusted by the fsw[4:0] bits of the boost-converter frequency register. the boost converter increases and decreases linearly with fsw[3:0]. to further reduce the amount of emi/efi generated by the circuit, the boost-converter frequency can be mod- ulated (see the ss[1:0] bits of the boost-converter fre- quency register). enabling modulation spreads the switching energy of the oscillator in the frequency domain, thus decreasing emi. independent dimming control the brightness of an el lamp is proportional to the peak-to-peak voltage applied across the lamp. the MAX14521E provides four registers to control the el peak-to-peak voltage of each el output using the el_ _[4:0] bits of the el ramping time and el peak volt- age registers. el output waveshape the MAX14521E can produce sine-wave to square- wave waveshapes on the el output by varying the slope of the el output. this is achieved by using bits sl[1:0] of the el shape register. if the el shape config- uration is set to sine and if all el outputs have the same amplitude settings, then each el output has a sinu- soidal waveshape. if the el outputs have different amplitude settings, then the el output with the highest setting has a sine waveshape while the remaining el outputs have a clamped sine waveshape. auxiliary audio input (aux) the MAX14521E uses an auxiliary input aux that accepts an audio signal to produce visual effects on the el outputs. the frequency and amplitude modula- tion (fr_am) bit is set to modulate the el output volt- age or frequency. the aux audio signal modulates the el output voltage when fr_am is set to 0 and modu- lates the el output frequency when fr_am is set to 1. when the no_sample bit is enabled, the voltage of the el outputs is proportional to the voltage at aux. for example, when fr_am = 0, no_sample = 1, and any of the au1, au2, au3, au4 bits are set to 1, the peak value of those particular channels follow aux directly. if aux is a dc value, the el output voltage is v el = 250 x aux (v p-p ) with a maximum of 300v p-p . aux can also accept a pwm signal with a frequency ranging from 100khz to 10mhz, where the el output voltage is v el = 300 x dutycycle% (v p-p ). the no_sample bit has no effect when fr_am = 1. when fr_am = 1, frequency modulation is enabled and the auxdiv1 and auxdiv0 bits are used to divide the audio frequency and apply this to the el outputs. au1, au2, au3, and au4 must be set to 1 to enable this feature. shutdown the MAX14521E features two methods to place the device in shutdown: 1) a reset input, rb, to clear all registers to zero and put the device into low-power shutdown mode, and 2) the en bit of the system regis- ter. using method 1, the device does not respond to i 2 c communications when rb is held low. using method 2, the el outputs are shut down; however, the register contents remain unchanged. undervoltage lockout (uvlo) the MAX14521E has a uvlo threshold of +2.0v (typ). when v dd falls below +2.0v (typ), the device enters a nonoperative mode. the contents of the i 2 c registers are not guaranteed below uvlo. thermal protection the MAX14521E enters a nonoperative mode if the internal die temperature of the device reaches or exceeds +160? (typ). the MAX14521E is latched, and only placing rb to 0 resets the thermal protection bit as well as all registers. MAX14521E quad, high-voltage el lamp driver with i 2 c interface 10 ______________________________________________________________________________________
MAX14521E quad, high-voltage el lamp driver with i 2 c interface ______________________________________________________________________________________ 11 i 2 c registers and bit descriptions ten internal registers program the MAX14521E. table 1 lists all the registers, their addresses, and power-on reset states. all registers are read/write. register 0x0a is reserved as a command to update all el peak volt- age output registers. register 0x0b is reserved and should not be written to. register b7 b6 b5 b4 b3 b2 b1 b0 register address power-on reset state system device id devid3 devid2 devid1 devid0 rev3 rev2 rev1 rev0 0x00 0xb2 power mode ovr temp* xxxxxxen 0x01 0x00 el frequency el output frequency fel7 fel6 fel5 fel4 fel3 fel2 fel1 fel0 0x02 0x00 el shape slope/shape x endamp x x s h ap e 1s h ap e 0 sl1 sl0 0x03 0x00 boost-converter frequency boost- c onver ter frequency ss1 ss0 x fsw4 fsw3 fsw2 fsw1 fsw0 0x04 0x00 audio audio effects fr_am no_ s am ple auxdiv1 auxdiv0 au4 au3 au2 au1 0x05 0x00 el ramping time and el peak voltage el1 ramping time and el peak voltage** rt1_2 rt1_1 rt1_0 el1_4 el1_3 el1_2 el1_1 el1_0 0x06 0x00 el2 ramping time and el peak voltage** rt2_2 rt2_1 rt2_0 el2_4 el2_3 el2_2 el2_1 el2_0 0x07 0x00 el3 ramping time and el peak voltage** rt3_2 rt3_1 rt3_0 el3_4 el3_3 el3_2 el3_1 el3_0 0x08 0x00 el4 ramping time and el peak voltage** rt4_2 rt4_1 rt4_0 el4_4 el4_3 el4_2 el4_1 el4_0 0x09 0x00 table 1. register map x = don? care * read back only. ** send command 0ah (update all el ramping time and el peak voltage registers) to have the programmed voltage effectively applied to the el lamp.
slave address the MAX14521E device address is set through external inputs. the slave address consists of five fixed bits (b7?3, set to 11110) followed by two input program- mable bits (a1 and a0). for example: if a1 and a0 are hardwired to ground, then the complete address is 1111000. the full address is defined as the seven most significant bits followed by the read/write bit. set the read/write bit to 1 to configure the MAX14521E to read mode. set the read/write bit to 0 to configure the MAX14521E to write mode. the address is the first byte of information sent to the MAX14521E after the start condition. system registers (0x00, 0x01) device id (devid3/devid2/devid1/devid0) devid[3:0] is preprogrammed to 1011 to identify the MAX14521E; see table 2. revision (rev3/rev2/rev1/rev0) rev[3:0] is preprogrammed to the current revision of the MAX14521E and is rev[3:0] = 0010. system overtemperature (ovrtemp) 1 = thermal shutdown temperature exceeded. 0 = analog circuitry operating properly. ovrtemp = 1 turns the el outputs off. to set ovrtemp to 0 and restart in default condition (all regis- ter reset), the user must place rb = 0. system enable (en) 1 = el outputs enabled. 0 = el outputs disabled. en = 1 places the MAX14521E in a normal operating mode. register contents are restored to values prior to shutdown. en = 0 disables the el outputs and places the device in a low-power shutdown state. el frequency register (0x02) el frequency (fel[7:0]) fel[7:6] sets the el frequency range of all el outputs and fel[5:0] sets the el frequency within the frequen- cy range; see table 4. fel[5:0] = 000000 sets the fre- quency to the minimum value of the frequency range. fel[5:0] = 111111 sets the frequency to the maximum value of the frequency range. el frequency increases linearly with fel[5:0]; see table 3. MAX14521E quad, high-voltage el lamp driver with i 2 c interface 12 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 0x00 devid3 devid2 devid1 devid0 rev3 rev2 rev1 rev0 0x01 ovrtemp x x x x x x en table 2. device identification, status, and enable register b7 b6 b5 b4 b3 b2 b1 b0 0x02 fel7 fel6 fel5 fel4 fel3 fel2 fel1 fel0 table 3. el output frequency fel[7:6] el fr eq u en c y ra n g e ( h z ) 00 50?00 01 100?00 10 200?00 11 400?00 table 4. el frequency range x = don? care
MAX14521E quad, high-voltage el lamp driver with i 2 c interface ______________________________________________________________________________________ 13 el shape register (0x03) damping enable (endamp) 1 = active damping on lx node enabled. 0 = active damping on lx node disabled. endamp = 1 actively damps the oscillation on the lx pin and could reduce emi. el shape (shape1/shape0) shape[1:0] sets the desired el output waveform; see tables 5 and 6. el slew rate (sl1/sl0) sl[1:0] sets the slope of the el output; see table 7. boost-converter frequency register (0x04) spread spectrum (ss1/ss0) ss[1:0] sets the spread-spectrum modulation frequen- cy to a fraction of the boost-converter frequency; see tables 8 and 9. boost-converter switching frequency (fsw[4:0]) fsw4 sets the switching frequency range of the boost converter and fsw[3:0] sets the switching frequency within the frequency range; see table 10. the frequency range for fsw4 = 0 is 800khz?600khz. the frequency range for fsw4 = 1 is 400khz?00khz. fsw[3:0] = 0000 sets the frequency to the minimum value of the fre- quency range. fsw[3:0] = 1111 sets the frequency to the maximum value of the frequency range. boost-con- verter switching frequency increases linearly with fsw[3:0]. register b7 b6 b5 b4 b3 b2 b1 b0 0x03 x endamp x x shape1 shape0 sl1 sl0 table 5. el shape configuration x = don? care x = don? care shape[1:0] el output shape 0x sine 10 do not use 11 do not use table 6. el output shape configuration sl[1:0] el output slope 00 sine 01 fast slope 10 faster slope 11 fastest slope (square wave) table 7. el slope configuration ss[1:0] spread spectrum 00 disabled 01 1/8 10 1/32 11 1/128 table 9. spread-spectrum configuration register b7 b6 b5 b4 b3 b2 b1 b0 0x04 ss1 ss0 x fsw4 fsw3 fsw2 fsw1 fsw0 table 8. boost-converter configurations x = don? care
MAX14521E quad, high-voltage el lamp driver with i 2 c interface 14 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 0x05 fr_am no_ sample auxdiv1 auxdiv0 au4 au3 au2 au1 table 11. audio input configurations boost-converter switching frequency (khz) fsw3 fsw2 fsw1 fsw0 fsw4 = 0 fsw4 = 1 0 0 0 0 800 400 0 0 0 1 853 427 0 0 1 0 907 453 0 0 1 1 960 480 0 1 0 0 1013 507 0 1 0 1 1067 533 0 1 1 0 1120 560 0 1 1 1 1173 587 1 0 0 0 1227 613 1 0 0 1 1280 640 1 0 1 0 1333 667 1 0 1 1 1387 693 1 1 0 0 1440 720 1 1 0 1 1493 747 1 1 1 0 1547 773 1 1 1 1 1600 800 table 10. boost-converter frequency range audio input register (0x05) frequency and amplitude modulation (fr_am) 0 = aux input signal modulates el output voltage. 1 = aux input frequency modulates el output frequency. aux envelope on el output (no_sample) 1 = the el output envelope follows that of the aux envelope. 0 = aux is sampled every f el cycle and the corre- sponding el output cycle has zero dc average. set fr_am = 0 when no_sample = 1 and enable the corresponding el outputs by bits au[4:1]. if fr_am = 1, the no_sample bit has no effect. if aux is a dc value, the el output peak-to-peak voltage is el_ (v p-p ) = 250 x aux (v) with a maximum of 300v p-p . if aux is a pwm signal with a frequency from 100khz to 10mhz, the el output voltage is v el = 300 x dutycycle% (v p-p ).
frequency divider (auxdiv1/auxdiv0) auxdiv[1:0] sets the divisor to divide down the aux input frequency; see table 12. audio enable (au4/au3/au2/au1) 1 = enable audio effect to el output. 0 = disable audio effect to el output. when fr_am = 0 the el outputs can be enabled and disabled independently according to au[4:1]. when fr_am = 1 then all au[4:1] bits must be set to 1 (i.e. au[4:1] = 1111) to enable the audio effect on the el outputs. el peak ramping time and el peak voltage register (0x06, 0x07, 0x08, 0x09) el ramping time (rt4_ _/rt3_ _/rt2_ _/rt1_ _) rt_ _[2:0] sets the ramp time of each el output; see table 14. el peak-to-peak voltage (el1_ _/el2_ _/ el3_ _/el4_ _) el _ _[4:0] controls the peak-to-peak voltage of each el output. when el _ _[4:0] = 00000, the el output fol- lows com. when el_ _[4:0] = 11111, the el output has a 150v peak with respect to com. the el output voltage rises linearly with el_ _[4:0]. i 2 c interface the MAX14521E features an i 2 c-compatible as a slave device, 2-wire serial interface consisting of a serial data line (sda) and a serial-clock line (scl). sda and scl facilitate communication to the device at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. a master device writes data to the MAX14521E by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the MAX14521E is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the MAX14521E transmits data on sda in sync with the master-generat- ed scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowl- edge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typi- cally greater than 500 , is required on scl if there are multiple masters on the bus, or if the master in a single- master system has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX14521E from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. MAX14521E quad, high-voltage el lamp driver with i 2 c interface ______________________________________________________________________________________ 15 auxdiv[1:0] aux frequency divider 00 16 01 8 10 4 11 2 table 12. aux frequency divider configuration rt_ _[2:0] ramping time (ms) 000 < 0.1 001 62.5 010 125 011 250 100 500 101 750 110 1000 111 2000 table 14. ramping time configuration register b7 b6 b5 b4 b3 b2 b1 b0 0x06 rt1_2 rt1_1 rt1_0 el1_4 el1_3 el1_2 el1_1 el1_0 0x07 rt2_2 rt2_1 rt2_0 el2_4 el2_3 el2_2 el2_1 el2_0 0x08 rt3_2 rt3_1 rt3_0 el3_4 el3_3 el3_2 el3_1 el3_0 0x09 rt4_2 rt4_1 rt4_0 el4_4 el4_3 el4_2 el4_1 el4_0 table 13. el output configuration
bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). sda and scl idle high when the i 2 c bus is not busy. start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start con- dition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 2). a start condition from the master signals the beginning of a transmission to the MAX14521E. the master terminates transmission and frees the bus by issuing a stop con- dition. the bus remains active if a repeated start condition is generated instead of a stop condition. early stop conditions the MAX14521E recognizes a stop condition at any point during data transmission except if the stop con- dition occurs in the same high pulse as a start condi- tion. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the MAX14521E has selectable device addresses through external inputs. the slave address consists of five fixed bits (b7?3, set to 11110) followed by two pin programmable bits (a1 and a0). for example: if a1 and a0 are hardwired to ground, the complete address is 1111000. the full address is defined as the seven most significant bits followed by the read/write bit. set the read/write bit to 1 to configure the MAX14521E to read mode. set the read/write bit to 0 to configure the MAX14521E to write mode. the address is the first byte of information sent to the MAX14521E after the start condition. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the MAX14521E uses to handshake receipt each byte of data when in write mode (see figure 3). the MAX14521E pull down sda during the entire master- generated 9th clock pulse if the previous byte is suc- cessfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a sys- tem fault had occurred. in the event of an unsuccessful data transfer, the bus master may retry communication. the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the MAX14521E are in read mode. an acknowledge is sent by the mas- ter after each read byte to allow data transfer to contin- ue. a not acknowledge is sent when the master reads the final byte of data from the MAX14521E followed by a stop condition. write data format a write to the MAX14521E includes transmission of a start condition, the slave address with the r/ w bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a stop condition. figure 4 illustrates the proper frame format for writing one byte of data to the MAX14521E. figure 5 illustrates the frame format for writing n-bytes of data to the MAX14521E. the slave address with the r/ w bit set to 0 indicates that the master intends to write data to the MAX14521E. the MAX14521E acknowledge receipt of the address byte during the master-generated 9th scl pulse. MAX14521E quad, high-voltage el lamp driver with i 2 c interface 16 ______________________________________________________________________________________ scl sda ssrp figure 2. start, stop, and repeated start conditions 1 scl start condition sda 289 clock pulse for acknowledgment acknowledge not acknowledge figure 3. acknowledge
MAX14521E quad, high-voltage el lamp driver with i 2 c interface ______________________________________________________________________________________ 17 a 0 slave address register address data byte acknowledge from MAX14521E r/w 1 byte autoincrement internal register address pointer acknowledge from MAX14521E acknowledge from MAX14521E b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 4. writing one byte of data to the MAX14521E 1 byte autoincrement internal register address pointer acknowledge from MAX14521E acknowledge from MAX14521E b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from MAX14521E r/w s a 1 byte acknowledge from MAX14521E b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n figure 5. writing n-bytes of data to the MAX14521E the second byte transmitted from the master config- ures the MAX14521E internal register address pointer. the pointer tells the MAX14521E where to write the next byte of data. an acknowledge pulse is sent by the MAX14521E upon receipt of the address pointer data. the third byte sent to the MAX14521E contains the data that will be written to the chosen register. an acknowledge pulse from the MAX14521E signals receipt of the data byte. the address pointer autoincre- ments to the next register address after each received data byte. this autoincrement feature allows a master to write to sequential registers within one continuous frame. attempting to write to register addresses higher than 0x0b results in repeated writes of 0x0b. figure 5 illustrates how to write to multiple registers with one frame. the master signals the end of transmission by issuing a stop condition.
MAX14521E quad, high-voltage el lamp driver with i 2 c interface 18 ______________________________________________________________________________________ acknowledge from MAX14521E 1 byte autoincrement internal register address pointer acknowledge from MAX14521E not acknowledge from master a a p a 0 acknowledge from MAX14521E r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 6. reading one indexed byte of data from the MAX14521E acknowledge from MAX14521E 1 byte autoincrement internal register address pointer acknowledge from MAX14521E a a ap 0 acknowledge from MAX14521E r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 7. reading n-bytes of indexed data from the MAX14521E read data format send the slave address with the r/ w set to 1 to initiate a read operation. the MAX14521E acknowledges receipt of its slave address by pulling sda low during the 9th scl clock pulse. a start command followed by a read command resets the address pointer to reg- ister 0x00. the first byte transmitted from the MAX14521E will be the contents of register 0x00. transmitted data is valid on the rising edge of the mas- ter-generated serial clock (scl). the address pointer autoincrements after each read data byte. this auto- increment feature allows all registers to be read sequentially within one continuous frame. a stop con- dition can be issued after any number of read data bytes. if a stop condition is issued followed by anoth- er read operation, the first data byte to be read will be from register 0x00 and subsequent reads will auto- increment the address pointer until the next stop con- dition. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the MAX14521E? slave address with the r/ w bit set to 0 followed by the register address. a repeated start condition is then sent, followed by the slave address with the r/ w set to 1. the MAX14521E transmits the contents of the specified register. the address pointer autoincrements after transmitting the first byte. attempting to read from register addresses higher than 0x0b results in repeated reads of 0x0b. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowl- edge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condition. figure 6 illustrates the frame format for reading one byte from the MAX14521E. figure 7 illustrates the frame format for reading multiple bytes from the MAX14521E.
MAX14521E quad, high-voltage el lamp driver with i 2 c interface ______________________________________________________________________________________ 19 charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 8a. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 8b. human body current waveform inductor value (?) vendor url part number 2.3/115 coilcraft www.coilcraft.com ga3250-bl 2.3/115 cooper www.cooper.com ctx03-18210-r table 15. inductor vendors esd test conditions esd performance depends on a number of conditions. the MAX14521E are specified for ?5kv (hbm) typical esd resistance on the el lamp outputs. hbm esd protection figure 8a shows the human body model, and figure 8b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the device through a 1.5k resistor. design procedure lx inductor selection the recommended tapped-inductor ratio is 1:7 with a 2.3? primary inductance and 115? secondary inductance. for most applications, the primary series resistance (dcr) should be below 1 for reasonable efficiency. do not exceed the inductor? saturation cur- rent. see table 15 for a list of recommended tapped- inductors.
c cs capacitor selection c cs is the output of the boost converter and provides the high-voltage source for the el lamp. connect a 3.3nf capacitor from cs to gnd and place as close to the cs input as possible. diode selection connect a diode, d1, from the lx node to cs to rectify the boost voltage on cs. the diode should be a fast recovery diode that is tolerant to +200v. el lamp selection el lamps have a capacitance of approximately 2.5nf to 3.5nf per square inch. see the total input current vs. load graph in the typical operating characteristics section for compatible lamp sizes. snubber selection an r sn value of 20 and c sn value of 330pf is suffi- cient for v dd < 5v and c lamp_total < 40nf. for higher capacitive loads on the el output or for v dd > 5v, c sn must be increased to keep lx spikes less than 30v. f sw selection choose a boost-converter frequency such that the sat- uration current of the tapped-inductor primary coil is not exceeded. special attention must be given to pro- gram the fsw bits properly when v bat > 5.5v to avoid destruction of the device. in general, it is good practice to start from the highest f sw setting (1.6mhz) and decrease accordingly to obtain the acquired wave- shape on the el outputs and to prevent exceeding the saturation current of the tapped-inductor. applications information pcb layout keep pcb traces as short as possible. ensure that bypass capacitors are as close to the device as possi- ble. use large ground planes where possible. chip information process: bicmos-dmos MAX14521E quad, high-voltage el lamp driver with i 2 c interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package type package code document no. 24 tqfn-ep t2444m-1 21-0139 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . MAX14521E *ep *exposed pad. connect ep to gnd. top view 2 17 3 16 4 15 5 14 i.c. gnd n.c. el4 lx 6 13 aux pgnd n.c. cs n.c. 1 18 n.c. el1 v dd sda scl rb 9 10 11 12 22 21 20 19 n.c. a1 8 23 el2 a0 7 24 n.c. com n.c. el3 tqfn-ep + pin configuration

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